Hi, Our CI found another issue, this time with vmx_pmu_caps_test. On 'Intel(R) Xeon(R) Gold 6328HL CPU' I see that all LBR msrs (from/to and TOS), are always read only - even when LBR is disabled - once I disable the feature in DEBUG_CTL, all LBR msrs reset to 0, and you can't change their value manually. Freeze LBRS on PMI seems not to affect this behavior. I don't know if this is how the hardware is supposed to work (Intel's manual doesn't mention anything about this), or if it is something platform specific, because this system also was found to have LBRs enabled (IA32_DEBUGCTL.LBR == 1) after a fresh boot, as if BIOS left them enabled - I don't have an idea on why. The problem is that vmx_pmu_caps_test writes 0 to LBR_TOS via KVM_SET_MSRS, and KVM actually passes this write to actual hardware msr (this is somewhat wierd), and since the MSR is not writable and silently drops writes instead, once the test tries to read it, it gets some random value instead. Any advice? Best regards, Maxim Levitsky
