Hi Daniel,
> > -/*
> > - * CPUTopoLevel is the general i386 topology hierarchical representation,
> > - * ordered by increasing hierarchical relationship.
> > - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
> > - * or AMD (CPUID[0x80000026]).
> > - */
> > -enum CPUTopoLevel {
> > - CPU_TOPO_LEVEL_INVALID,
> > - CPU_TOPO_LEVEL_SMT,
> > - CPU_TOPO_LEVEL_CORE,
> > - CPU_TOPO_LEVEL_MODULE,
> > - CPU_TOPO_LEVEL_DIE,
> > - CPU_TOPO_LEVEL_PACKAGE,
> > - CPU_TOPO_LEVEL_MAX,
> > -};
> > -
>
> snip
>
> > @@ -18,3 +18,47 @@
> > ##
> > { 'enum': 'S390CpuEntitlement',
> > 'data': [ 'auto', 'low', 'medium', 'high' ] }
> > +
> > +##
> > +# @CpuTopologyLevel:
> > +#
> > +# An enumeration of CPU topology levels.
> > +#
> > +# @invalid: Invalid topology level.
>
> Previously all topology levels were internal to QEMU, and IIUC
> this CPU_TOPO_LEVEL_INVALID appears to have been a special
> value to indicate the cache was absent ?
Now I haven't support this logic.
x86 CPU has a "l3-cache" property, and maybe that property can be
implemented or replaced by the "invalid" level support you mentioned.
> Now we're exposing this directly to the user as a settable
> option. We need to explain what effect setting 'invalid'
> has on the CPU cache config.
If user set "invalid", QEMU will report the error message:
qemu-system-x86_64: Invalid cache topology level: invalid. The topology should match valid CPU topology level
Do you think this error message is sufficient?
Thanks,
Zhao
