RESEND (again, sorry) as didn't reach list.
Issue some stray " in various email addresses.
On Sat, 12 Oct 2024 18:44:22 +0800
Zhao Liu <zhao1.liu@xxxxxxxxx> wrote:
> Hi all,
>
> Compared with v2 [1], the changes in v3 are quite minor, and most of
> patches (except for patch 1 and 7) have received Jonathan’s R/b (thanks
> Jonathan!).
>
> Meanwhile, ARM side has also worked a lot on the smp-cache based on
> this series [2], so I think we are very close to the final merge, to
> catch up with this cycle. :)
This would finally solve a long standing missing control for our
virtualization usecases (TCG and MPAM stuff is an added bonus),
so I'm very keen in this making 9.2 (and maybe even the ARM part
of things happen to move fast enough). Ali is out this week,
but should be back sometime next week. Looks like rebase of his
ARM patches on this should be simple!
I think this set mostly needs a QAPI review (perhaps from Markus?)
>
> This series is based on the commit 7e3b6d8063f2 ("Merge tag 'crypto-
> fixes-pull-request' of https://gitlab.com/berrange/qemu into staging").
>
> Background
> ==========
>
> The x86 and ARM (RISCV) need to allow user to configure cache properties
*laughs*. I definitely going to start emailing ARM folk with
ARM (RISCV)
:)
> (current only topology):
> * For x86, the default cache topology model (of max/host CPU) does not
> always match the Host's real physical cache topology. Performance can
> increase when the configured virtual topology is closer to the
> physical topology than a default topology would be.
> * For ARM, QEMU can't get the cache topology information from the CPU
> registers, then user configuration is necessary. Additionally, the
> cache information is also needed for MPAM emulation (for TCG) to
> build the right PPTT. (Originally from Jonathan)
