On Wed, Oct 09, 2024 at 01:23:15PM -0300, Jason Gunthorpe wrote: > Force Write Back (FWB) changes how the S2 IOPTE's MemAttr field > works. When S2FWB is supported and enabled the IOPTE will force cachable > access to IOMMU_CACHE memory when nesting with a S1 and deny cachable > access otherwise. > > When using a single stage of translation, a simple S2 domain, it doesn't > change things for PCI devices as it is just a different encoding for the > existing mapping of the IOMMU protection flags to cachability attributes. > For non-PCI it also changes the combining rules when incoming transactions > have inconsistent attributes. > > However, when used with a nested S1, FWB has the effect of preventing the > guest from choosing a MemAttr in it's S1 that would cause ordinary DMA to > bypass the cache. Consistent with KVM we wish to deny the guest the > ability to become incoherent with cached memory the hypervisor believes is > cachable so we don't have to flush it. > > Allow NESTED domains to be created if the SMMU has S2FWB support and use > S2FWB for NESTING_PARENTS. This is an additional option to CANWBS. > > Signed-off-by: Jason Gunthorpe <jgg@xxxxxxxxxx> My HW doesn't support this S2FWB for testing, but the patch LGTM. Reviewed-by: Nicolin Chen <nicolinc@xxxxxxxxxx> > @@ -265,6 +266,7 @@ static inline u32 arm_smmu_strtab_l2_idx(u32 sid) > #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) > > #define STRTAB_STE_1_S1STALLD (1UL << 27) > +#define STRTAB_STE_1_S2FWB (1UL << 25) Nit: seems that it should be in ascending order. Thanks Nicolin
