For hybrid cpu topology, Intel exposes these CPUIDs [1]:
1. Set CPUID.07H.0H:EDX.Hybrid[bit 15]. With setting as 1, the processor
is identified as a hybrid part.
2. Have CPUID.1AH leaf. Set core type and native model ID in
CPUID.1AH:EAX. Because the native model ID is currently useless for
the software, no need to emulate.
For hybrid related CPUIDs, especially CPUID.07H.0H:EDX.Hybrid[bit 15],
there's no need to expose this feature in feature_word_info[] to allow
user to set directly, because hybrid features depend on the specific
core type information, and this information needs to be gathered
together with hybrid cpu topology.
[1]: SDM, vol.2, Ch.3, 3.2 Instructions (A-L), CPUID-CPU Identification
Co-Developed-by: Zhuocheng Ding <zhuocheng.ding@xxxxxxxxx>
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@xxxxxxxxx>
Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
---
target/i386/cpu.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 5 ++++
2 files changed, 63 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fb54c2c100a0..2f0e7f3d5ad7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -22,6 +22,7 @@
#include "qemu/cutils.h"
#include "qemu/qemu-print.h"
#include "qemu/hw-version.h"
+#include "core.h"
#include "cpu.h"
#include "tcg/helper-tcg.h"
#include "sysemu/hvf.h"
@@ -743,6 +744,10 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_AMX_TMUL_MAX_K 0x10
#define INTEL_AMX_TMUL_MAX_N 0x40
+/* CPUID Leaf 0x1A constants: */
+#define INTEL_HYBRID_TYPE_ATOM 0x20
+#define INTEL_HYBRID_TYPE_CORE 0x40
+
void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
{
@@ -6580,6 +6585,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx |= CPUID_7_0_ECX_OSPKE;
}
*edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
+
+ if (env->parent_core_type != COMMON_CORE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ *edx |= CPUID_7_0_EDX_HYBRID;
+ }
} else if (count == 1) {
*eax = env->features[FEAT_7_1_EAX];
*edx = env->features[FEAT_7_1_EDX];
@@ -6800,6 +6810,31 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
break;
}
+ case 0x1A:
+ /* Hybrid Information Enumeration */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (env->parent_core_type != COMMON_CORE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ /*
+ * CPUID.1AH:EAX.[bits 23-0] indicates "native model ID of the
+ * core". Since this field currently is useless for software,
+ * no need to emulate.
+ */
+ switch (env->parent_core_type) {
+ case INTEL_ATOM:
+ *eax = INTEL_HYBRID_TYPE_ATOM << 24;
+ break;
+ case INTEL_CORE:
+ *eax = INTEL_HYBRID_TYPE_CORE << 24;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ break;
case 0x1D: {
/* AMX TILE, for now hardcoded for Sapphire Rapids*/
*eax = 0;
@@ -7459,6 +7494,14 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
}
}
+ /*
+ * Intel CPU topology with hybrid cores support requires CPUID.1AH.
+ */
+ if (env->parent_core_type != COMMON_CORE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1A);
+ }
+
/*
* Intel CPU topology with multi-dies support requires CPUID[0x1F].
* For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
@@ -7650,6 +7693,20 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
+ /*
+ * TODO: Introduce parent_pre_realize to make sure topology device
+ * can realize first.
+ */
+ if (dev->parent_bus && dev->parent_bus->parent) {
+ DeviceState *parent = dev->parent_bus->parent;
+ X86CPUCore *core =
+ (X86CPUCore *)object_dynamic_cast(OBJECT(parent),
+ TYPE_X86_CPU_CORE);
+ if (core) {
+ env->parent_core_type = X86_CPU_CORE_GET_CLASS(core)->core_type;
+ }
+ }
+
/*
* Process Hyper-V enlightenments.
* Note: this currently has to happen before the expansion of CPU features.
@@ -8048,6 +8105,7 @@ static void x86_cpu_initfn(Object *obj)
CPUX86State *env = &cpu->env;
x86_cpu_init_default_topo(cpu);
+ env->parent_core_type = COMMON_CORE;
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
x86_cpu_get_feature_words,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index afe2b5fd3382..38236df547e6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -21,6 +21,7 @@
#define I386_CPU_H
#include "sysemu/tcg.h"
+#include "core.h"
#include "cpu-qom.h"
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
@@ -920,6 +921,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
/* SERIALIZE instruction */
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
+/* Hybrid */
+#define CPUID_7_0_EDX_HYBRID (1U << 15)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* Architectural LBRs */
@@ -1996,6 +1999,8 @@ typedef struct CPUArchState {
/* Bitmap of available CPU topology levels for this CPU. */
DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
+
+ X86CoreType parent_core_type;
} CPUX86State;
struct kvm_msrs;
--
2.34.1
