On Tue, Sep 10, 2024, Paolo Bonzini wrote: > On 9/4/24 05:07, Rick Edgecombe wrote: > > From: Isaku Yamahata <isaku.yamahata@xxxxxxxxx> > > > > Although TDX supports only WB for private GPA, it's desirable to support > > MTRR for shared GPA. Always honor guest PAT for shared EPT as what's done > > for normal VMs. > > > > Suggested-by: Kai Huang <kai.huang@xxxxxxxxx> > > Co-developed-by: Yan Zhao <yan.y.zhao@xxxxxxxxx> > > Signed-off-by: Yan Zhao <yan.y.zhao@xxxxxxxxx> > > Signed-off-by: Isaku Yamahata <isaku.yamahata@xxxxxxxxx> > > Signed-off-by: Rick Edgecombe <rick.p.edgecombe@xxxxxxxxx> > > --- > > TDX MMU part 2 v1: > > - Align with latest vmx code in kvm/queue. > > - Updated patch log. > > - Dropped KVM_BUG_ON() in vt_get_mt_mask(). (Rick) > > The only difference at this point is > > if (!static_cpu_has(X86_FEATURE_SELFSNOOP) && > !kvm_arch_has_noncoherent_dma(vcpu->kvm)) > return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | > VMX_EPT_IPAT_BIT; > > > which should never be true. I think this patch can simply be dropped. And we can/should do what we've done for SEV, and make it a hard dependency to enable TDX, e.g. similar to this: /* * SEV must obviously be supported in hardware. Sanity check that the * CPU supports decode assists, which is mandatory for SEV guests to * support instruction emulation. Ditto for flushing by ASID, as SEV * guests are bound to a single ASID, i.e. KVM can't rotate to a new * ASID to effect a TLB flush. */ if (!boot_cpu_has(X86_FEATURE_SEV) || WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) || WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_FLUSHBYASID))) goto out;
