Baolu, On 8/16/2024 8:19 AM, Baolu Lu wrote: > On 8/16/24 9:19 AM, Yi Liu wrote: >> On 2024/8/16 01:49, Vasant Hegde wrote: >>> Hi All, >>> >>> On 6/28/2024 2:25 PM, Yi Liu wrote: >>>> This splits the preparation works of the iommu and the Intel iommu driver >>>> out from the iommufd pasid attach/replace series. [1] >>>> >>>> To support domain replacement, the definition of the set_dev_pasid op >>>> needs to be enhanced. Meanwhile, the existing set_dev_pasid callbacks >>>> should be extended as well to suit the new definition. >>> >>> IIUC this will remove PASID from old SVA domain and attaches to new SVA domain. >>> (basically attaching same dev/PASID to different process). Is that the correct? >> >> In brief, yes. But it's not only for SVA domain. Remember that SIOVr1 >> extends the usage of PASID. At least on Intel side, a PASID may be >> attached to paging domains. > > You are correct. Thanks. > > The idxd driver attaches a paging domain to a non-zero PASID for kernel > DMA with PASID. From an architectural perspective, other architectures, > like ARM, AMD, and RISC-V, also support this. Therefore, attaching a > paging domain to a PASID is not Intel-specific but a generic feature. Right. We can enhance AMD driver to support attaching PASID to paging/UNMANAGED domains. It needs some more rework/cleanup before we do that. -Vasant
