On Tue, Aug 06, 2024, Paolo Bonzini wrote: > On Tue, Aug 6, 2024 at 6:03 PM Sean Christopherson <seanjc@xxxxxxxxxx> wrote: > > > As is noted in [1], this issue is considered to be a microcode issue > > > specific to SPR/EMR. > > > > I don't think we can claim that without a more explicit statement from Intel. > > And I would really like Intel to clarify exactly what is going on, so that (a) > > it can be properly documented and (b) we can implement a precise, targeted > > workaround in KVM. > > It is not even clear to me why this patch has any effect at all, > because PV EOI and APICv don't work together anyway: PV EOI requires > apic->highest_isr_cache == -1 (see apic_sync_pv_eoi_to_guest()) but > the cache is only set without APICv (see apic_set_isr()). Therefore, > PV EOI should be basically a no-op with APICv in use. Per Chao, this is a ucode bug though. Speculating wildly, I wonder if Intel added acceleration and/or redirection of HV_X64_MSR_EOI when APICv is enabled, e.g. to speed up existing VMs, and something went sideways.
