On 7/19/24 13:25, Marc Zyngier wrote:
> On Thu, 18 Jul 2024 22:55:32 +0100,
> Raghavendra Rao Ananta <rananta@xxxxxxxxxx> wrote:
>>
>> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
>> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
>> Hence, correct them to reflect ARM ARM.
>>
>> Signed-off-by: Raghavendra Rao Ananta <rananta@xxxxxxxxxx>
>> ---
>> arch/arm64/tools/sysreg | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -149,7 +149,7 @@ Res0 63:32
>> UnsignedEnum 31:28 GIC
>> 0b0000 NI
>> 0b0001 GICv3
>> - 0b0010 GICv4p1
>> + 0b0011 GICv4p1
>> EndEnum
>> UnsignedEnum 27:24 Virt_frac
>> 0b0000 NI
>> @@ -903,7 +903,7 @@ EndEnum
>> UnsignedEnum 27:24 GIC
>> 0b0000 NI
>> 0b0001 IMP
>> - 0b0010 V4P1
>> + 0b0011 V4P1
>
> I wonder why we have different naming schemes for the same feature...
Both definitions were added via different commits and different developers who
might just have interpreted the following common description bit differently.
"System register interface to version 4.1 of the GIC CPU interface is supported"
1224308075f1 ("arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation")
cea08f2bf406 ("arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation")
But I agree that same fields should be named exactly the same both in their 32
bit and 64 bit variants.
>
>> EndEnum
>> SignedEnum 23:20 AdvSIMD
>> 0b0000 IMP
>>
>
> Yup, this looks correct and checks out against revision H.b of the GICv3
> spec, revision K.a of the ARM ARM, and even I.a (which the original
> patches were referencing).
>
> Once more, it shows that these dumps should be automatically generated
> from the XML instead of (creatively) hand-written.
>
> Reviewed-by: Marc Zyngier <maz@xxxxxxxxxx>
>
> M.
>
