Marc Zyngier <maz@xxxxxxxxxx> writes:
> On 2024-07-03 08:09, Zenghui Yu wrote:
>> On 2024/7/3 0:35, Alex Bennée wrote:
>>> The test for number of events is not a substitute for properly
>>> checking the feature register. Fix the define and skip if PMUv3 is not
>>> available on the system. This includes emulator such as QEMU which
>>> don't implement PMU counters as a matter of policy.
>>> Signed-off-by: Alex Bennée <alex.bennee@xxxxxxxxxx>
>>> Cc: Anders Roxell <anders.roxell@xxxxxxxxxx>
>>> ---
>>> arm/pmu.c | 7 ++++++-
>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>> diff --git a/arm/pmu.c b/arm/pmu.c
>>> index 9ff7a301..66163a40 100644
>>> --- a/arm/pmu.c
>>> +++ b/arm/pmu.c
>>> @@ -200,7 +200,7 @@ static void test_overflow_interrupt(bool
>>> overflow_at_64bits) {}
>>> #define ID_AA64DFR0_PERFMON_MASK 0xf
>>> #define ID_DFR0_PMU_NOTIMPL 0b0000
>>> -#define ID_DFR0_PMU_V3 0b0001
>>> +#define ID_DFR0_PMU_V3 0b0011
>> Why? This is a macro used for AArch64 and DDI0487J.a (D19.2.59, the
>> description of the PMUVer field) says that
>> "0b0001 Performance Monitors Extension, PMUv3 implemented."
>> while 0b0011 is a reserved value.
>
> I think this is a mix of 32bit and 64bit views (ID_DFR0_EL1.PerfMon
> instead of ID_AA64DFR0_EL1.PMUVer), and the whole thing is a mess
> (ID_AA64DFR0_PERFMON_MASK is clearly confused...).
>
> I haven't looked at how this patch fits in the rest of the code
> though.
Doh - yes different set of values for 32 bit.
>
> M.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
