On Wed, Jun 26, 2024 at 9:39 AM Conor Dooley <conor@xxxxxxxxxx> wrote: > > On Wed, Jun 26, 2024 at 05:37:07PM +0100, Conor Dooley wrote: > > On Wed, Jun 26, 2024 at 09:18:46AM -0700, Atish Kumar Patra wrote: > > > On Wed, Jun 26, 2024 at 6:24 AM Samuel Holland > > > <samuel.holland@xxxxxxxxxx> wrote: > > > > > > > > On 2024-06-26 2:23 AM, Atish Patra wrote: > > > > > From: Samuel Holland <samuel.holland@xxxxxxxxxx> > > > > > > > > > > Currently, we stop all the counters while a new cpu is brought online. > > > > > However, the hpmevent to counter mappings are not reset. The firmware may > > > > > have some stale encoding in their mapping structure which may lead to > > > > > undesirable results. We have not encountered such scenario though. > > > > > > > > > > > > > This needs: > > > > > > > > Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx> > > > > > > > > > > Oops. Sorry I missed that. > > > > > > @Alexandre Ghiti > > > > What's Alex going to be able to do? > > He is collecting the fixes patches in the RISC-V tree and pinged for revision for this patch last week. > > > @Palmer Dabbelt : Can you add that while picking up > > > the patch or should I respin a v4 ? > > > > b4 should pick the signoff up though. "perf: RISC-V: Check standard > > event availability" seems to be missing your signoff though... > > Huh, this doesn't really make sense. I meant: > b4 should pick the signoff up, though "perf: RISC-V: Check standard > event availability" seems to be missing your signoff... Strange. I modified and sent the patch using b4 as well. It's missing my sign off too.
