Currently interrupt is posted and cleared with async mode, and it is saved
in SW state vcpu::arch::irq_pending and vcpu::arch::irq_clear. When vcpu
is ready to run, interrupt is synced to ESTAT CSR register from SW state
vcpu::arch::irq_pending at guest entrance.
During VM migration stage, vcpu is put into stopped state, however
pending interrupt is not synced to ESTAT CSR register. So there will be
interrupt lost when VCPU is stopped and migrated to other host machines.
Here when ESTAT CSR register is read from VMM user mode, pending
interrupt is synced to ESTAT also. So that VMM can get correct pending
interrupt.
Signed-off-by: Bibo Mao <maobibo@xxxxxxxxxxx>
---
arch/loongarch/kvm/vcpu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
index b747bd8bc037..81622cd055af 100644
--- a/arch/loongarch/kvm/vcpu.c
+++ b/arch/loongarch/kvm/vcpu.c
@@ -371,9 +371,18 @@ static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val)
return -EINVAL;
if (id == LOONGARCH_CSR_ESTAT) {
+ preempt_disable();
+ vcpu_load(vcpu);
+ /*
+ * Sync pending interrupt into estat so that interrupt
+ * remains during migration stage
+ */
+ kvm_deliver_intr(vcpu);
/* ESTAT IP0~IP7 get from GINTC */
gintc = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff;
*val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2);
+ vcpu_put(vcpu);
+ preempt_enable();
return 0;
}
base-commit: 92e5605a199efbaee59fb19e15d6cc2103a04ec2
--
2.39.3
