On Thu, 13 Jun 2024 21:17:44 +0100,
Oliver Upton <oliver.upton@xxxxxxxxx> wrote:
>
> From: Marc Zyngier <maz@xxxxxxxxxx>
>
> Handle CPACR_EL1 accesses when running a VHE guest. In order to
> limit the cost of the emulation, implement it ass a shallow exit.
>
> In the other cases:
>
> - this is a nVHE L1 which will write to memory, and we don't trap
>
> - this is a L2 guest:
>
> * the L1 has CPTR_EL2.TCPAC==0, and the L2 has direct register
> access
>
> * the L1 has CPTR_EL2.TCPAC==1, and the L2 will trap, but the
> handling is defered to the general handling for forwarding
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> Signed-off-by: Oliver Upton <oliver.upton@xxxxxxxxx>
> ---
> arch/arm64/kvm/hyp/vhe/switch.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
> index d7af5f46f22a..fed36457fef9 100644
> --- a/arch/arm64/kvm/hyp/vhe/switch.c
> +++ b/arch/arm64/kvm/hyp/vhe/switch.c
> @@ -262,10 +262,40 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
> return true;
> }
>
> +static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
> +{
> + u64 esr = kvm_vcpu_get_esr(vcpu);
> + int rt;
> +
> + if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1)
> + return false;
> +
> + rt = kvm_vcpu_sys_get_rt(vcpu);
> +
> + if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) {
> + vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2));
> + } else {
> + vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
> + __activate_cptr_traps(vcpu);
This doesn't bisect, as this helper is only introduced in patch #10.
You probably want to keep it towards the end of the series.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
