On Mon Jun 3, 2024 at 6:26 PM AEST, Thomas Huth wrote: > On 02/06/2024 14.25, Nicholas Piggin wrote: > > Unless make V=1 is specified, silence make recipe echoing and print > > an abbreviated line for major build steps. > > > > Signed-off-by: Nicholas Piggin <npiggin@xxxxxxxxx> > > --- > > Makefile | 14 ++++++++++++++ > > arm/Makefile.common | 7 +++++++ > > powerpc/Makefile.common | 11 +++++++---- > > riscv/Makefile | 5 +++++ > > s390x/Makefile | 18 +++++++++++++++++- > > scripts/mkstandalone.sh | 2 +- > > x86/Makefile.common | 5 +++++ > > 7 files changed, 56 insertions(+), 6 deletions(-) > > The short lines look superfluous in verbose mode, e.g.: > > [OBJCOPY] s390x/memory-verify.bin > objcopy -O binary s390x/memory-verify.elf s390x/memory-verify.bin > > Could we somehow suppress the echo lines in verbose mode, please? > > For example in the SLOF project, it's done like this: > > https://gitlab.com/slof/slof/-/blob/master/make.rules?ref_type=heads#L48 > > By putting the logic into $CC and friends, you also don't have to add > "@echo" statements all over the place. I'll could try a bit harder at it, this was a pretty quick hack. I probably prefer the cmd_cc style that Linux uses rather than overloading CC. But maybe that's more work. Thanks, Nick
