On Sat, 01 Jun 2024 00:13:47 +0100, Oliver Upton <oliver.upton@xxxxxxxxx> wrote: > > Hey! > > I've decided to start messing around with nested and have SVE support > working for a nested guest. For the sake of landing a semi-complete > feature upstream, I've also picked up the FPSIMD patches from the NV > series Marc is carrying. > > The most annoying part about this series (IMO) is that ZCR_EL2 traps > behave differently from what needs to be virtualized for the guest when > HCR_EL2.NV = 1, as it takes a sysreg trap (EC = 0x18) instead of an SVE > trap (EC = 0x19). So, we need to synthesize the ESR value when > reflecting back into the guest hypervisor. That's unfortunately not a unique case. The ERETAx emulation already requires us to synthesise the ESR on PAC check failure, and I'm afraid ZCR_EL2 might not be the last case. In general, we'll see this problem for any instruction or sysreg that can generate multiple exception classes. > > Otherwise, some care is required to slap the guest hypervisor's ZCR_EL2 > into the right place depending on whether or not the vCPU is in a hyp > context, since it affects the hyp's usage of SVE in addition to the VM. > > There's more work to be done for honoring the L1's CPTR traps, as this > series only focuses on getting SVE and FPSIMD traps right. We'll get > there one day. I have patches for that in my NV series, which would take the place of patches 9 and 10 in your series (or supplement them, depending on how we want to slice this). > > I tested this using a mix of the fpsimd-test and sve-test selftests > running at L0, L1, and L2 concurrently on Neoverse V2. Thanks a lot for tackling this. It'd be good to put together a series that has the EL2 sysreg save/restore patches as a prefix of this, plus the CPTR_EL2 changes. That way, we'd have something that can be merged as a consistent set. I'll try to take this into my branch and see what explodes! Cheers, M. -- Without deviation from the norm, progress is not possible.
