On Tue, May 07, 2024, Chen, Zide wrote: > > > On 5/5/2024 10:29 PM, Mingwei Zhang wrote: > > From: Xiong Zhang <xiong.y.zhang@xxxxxxxxxxxxxxx> > > > > Add x86 specific function to switch PMI handler since passthrough PMU and host > > PMU use different interrupt vectors. > > > > x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, > > and guest LVTPC_MASK value should be reflected onto HW to indicate whether > > guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. > > > > x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. > > > > Signed-off-by: Xiong Zhang <xiong.y.zhang@xxxxxxxxxxxxxxx> > > Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx> > > --- > > arch/x86/events/core.c | 17 +++++++++++++++++ > > arch/x86/include/asm/perf_event.h | 3 +++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > > index 09050641ce5d..8167f2230d3a 100644 > > --- a/arch/x86/events/core.c > > +++ b/arch/x86/events/core.c > > @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) > > } > > EXPORT_SYMBOL_GPL(perf_guest_get_msrs); > > > > +void x86_perf_guest_enter(u32 guest_lvtpc) > > +{ > > + lockdep_assert_irqs_disabled(); > > + > > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | > > + (guest_lvtpc & APIC_LVT_MASKED)); > > If CONFIG_KVM is not defined, KVM_GUEST_PMI_VECTOR is not available and > it causes compiling error. That is a good discovery, thanks. hmm, we could put the whole function under IS_ENABLED(CONFIG_KVM) to avoid that. Thanks. -Mingwei