From: Sandipan Das <sandipan.das@xxxxxxx> If passthrough PMU is enabled and all counters exposed to guest, clear the RDPMC interception bit in the VMCB Control Area (byte offset 0xc bit 15) to let RDPMC instructions proceed without VM-Exits. This improves the guest PMU performance in passthrough mode. If either condition is not satisfied, then intercept RDPMC and prevent guest accessing unexposed counters. Note that On AMD platforms, passing through RDPMC will only allow guests to read the general-purpose counters. Details about the RDPMC interception bit can be found in Appendix B the "Layout of VMCB" from the AMD64 Architecture Programmer's Manual Volume 2. Signed-off-by: Sandipan Das <sandipan.das@xxxxxxx> --- arch/x86/kvm/svm/svm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 88648b3a9cdd..84dd1f560d0a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1223,6 +1223,11 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) /* No need to intercept these MSRs */ set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); + + if (kvm_pmu_check_rdpmc_passthrough(vcpu)) + svm_clr_intercept(svm, INTERCEPT_RDPMC); + else + svm_set_intercept(svm, INTERCEPT_RDPMC); } } -- 2.45.0.rc1.225.g2a3ae87e7f-goog
