On Thu, 2024-03-21 at 09:37 -0700, Reinette Chatre wrote: > From: Isaku Yamahata <isaku.yamahata@xxxxxxxxx> > > Introduce the VM variable "nanoseconds per APIC bus cycle" in > preparation to make the APIC bus frequency configurable. > > The TDX architecture hard-codes the core crystal clock frequency to > 25MHz and mandates exposing it via CPUID leaf 0x15. The TDX architecture > does not allow the VMM to override the value. > > In addition, per Intel SDM: > "The APIC timer frequency will be the processor’s bus clock or core > crystal clock frequency (when TSC/core crystal clock ratio is > enumerated in CPUID leaf 0x15) divided by the value specified in > the divide configuration register." > > The resulting 25MHz APIC bus frequency conflicts with the KVM hardcoded > APIC bus frequency of 1GHz. > > Introduce the VM variable "nanoseconds per APIC bus cycle" to prepare > for allowing userspace to tell KVM to use the frequency that TDX mandates > instead of the default 1Ghz. Doing so ensures that the guest doesn't have > a conflicting view of the APIC bus frequency. > > Signed-off-by: Isaku Yamahata <isaku.yamahata@xxxxxxxxx> > Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx> > [reinette: rework changelog] > Signed-off-by: Reinette Chatre <reinette.chatre@xxxxxxxxx> Reviewed-by: Rick Edgecombe <rick.p.edgecombe@xxxxxxxxx>
