On Thu, Apr 11, 2024 at 3:54 PM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
>
> On Thu, Apr 11, 2024, Jim Mattson wrote:
> > On Thu, Apr 11, 2024 at 2:54 PM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
> > >
> > > On Fri, Jan 26, 2024, Xiong Zhang wrote:
> > > > +static void save_perf_global_ctrl_in_passthrough_pmu(struct vcpu_vmx *vmx)
> > > > +{
> > > > + struct kvm_pmu *pmu = vcpu_to_pmu(&vmx->vcpu);
> > > > + int i;
> > > > +
> > > > + if (vm_exit_controls_get(vmx) & VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) {
> > > > + pmu->global_ctrl = vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL);
> > > > + } else {
> > > > + i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest,
> > > > + MSR_CORE_PERF_GLOBAL_CTRL);
> > > > + if (i < 0)
> > > > + return;
> > > > + pmu->global_ctrl = vmx->msr_autostore.guest.val[i].value;
> > >
> > > As before, NAK to using the MSR load/store lists unless there's a *really* good
> > > reason I'm missing.
> >
> > The VM-exit control, "save IA32_PERF_GLOBAL_CTL," first appears in
> > Sapphire Rapids. I think that's a compelling reason.
>
> Well that's annoying. When was PMU v4 introduced? E.g. if it came in ICX, I'd
> be sorely tempted to make VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL a hard requirement.
Broadwell was v3. Skylake was v4.
> And has someone confirmed that the CPU saves into the MSR store list before
> processing VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL?
It's at the top of chapter 28 in volume 3 of the SDM. MSRs may be
saved in the VM-exit MSR-store area before processor state is loaded
based in part on the host-state area and some VM-exit controls.
Anything else would be stupid. (Yes, I know that this is CPU design
we're talking about!)
