The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension,
to prevent RW operations to the missing CSRs, which will cause
illegal instructions.
As a solution, we have proposed the dt format for these CSRs.
Signed-off-by: Max Hsu <max.hsu@xxxxxxxxxx>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b..c713a48c5025 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -137,6 +137,24 @@ properties:
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
+ debug:
+ type: object
+ properties:
+ compatible:
+ const: riscv,debug-v1.0.0
+ trigger-module:
+ type: object
+ description: |
+ An indication set of optional CSR existence from
+ riscv-debug-spec Sdtrig extension
+ properties:
+ mcontext-present:
+ type: boolean
+ hcontext-present:
+ type: boolean
+ scontext-present:
+ type: boolean
+
anyOf:
- required:
- riscv,isa
--
2.43.2
