On Mon, Mar 25, 2024 at 09:23:18AM +0000, Marc Zyngier wrote: > Mark Brown <broonie@xxxxxxxxxx> wrote: > > This was referring to the fact that currently when SVE is enabled access > > to the V registers as V registers via _CORE_REG() is blocked and they > > can only be accessed as a subset of the Z registers (see the check at > > the end of core_reg_size_from_offset() in guest.c). > But what behaviour do you expect from allowing such a write? Insert in > place? Or zero the upper bits of the vector, as per R_WKYLB? One is > wrong, and the other wrecks havoc on unsuspecting userspace. It would have to be the former due to the ABI issue I think. > My take on this is that when a VM is S*E aware, only the writes to the > largest *enabled* registers should take place. This is similar to what > we do for FP/SIMD: we only allow writes to the V registers, and not to > Q, D, S, H or B, although that happens by construction. For S*E, > dropping the write on the floor (or return some error that userspace > will understand as benign) is the least bad option. OK, this does mean that in the case of a SME only guest we'll end up with registers not just changing size but appearing and disappearing depending on SVCR.SM. It wasn't clear to me that this was a good idea from an ABI point of view, it's a level up beyond the size changing thing and there's a tradeoff with the "model what the architecture does" model.
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