On Thu, Feb 29, 2024 at 11:44 PM Sandipan Das <sandipan.das@xxxxxxx> wrote:
>
> On AMD and Hygon platforms, the local APIC does not automatically set
> the mask bit of the LVTPC register when handling a PMI and there is
> no need to clear it in the kernel's PMI handler.
I don't know why it didn't occur to me that different x86 vendors
wouldn't agree on this specification. :)
> For guests, the mask bit is currently set by kvm_apic_local_deliver()
> and unless it is cleared by the guest kernel's PMI handler, PMIs stop
> arriving and break use-cases like sampling with perf record.
>
> This does not affect non-PerfMonV2 guests because PMIs are handled in
> the guest kernel by x86_pmu_handle_irq() which always clears the LVTPC
> mask bit irrespective of the vendor.
>
> Before:
>
> $ perf record -e cycles:u true
> [ perf record: Woken up 1 times to write data ]
> [ perf record: Captured and wrote 0.001 MB perf.data (1 samples) ]
>
> After:
>
> $ perf record -e cycles:u true
> [ perf record: Woken up 1 times to write data ]
> [ perf record: Captured and wrote 0.002 MB perf.data (19 samples) ]
>
> Fixes: a16eb25b09c0 ("KVM: x86: Mask LVTPC when handling a PMI")
> Signed-off-by: Sandipan Das <sandipan.das@xxxxxxx>
> ---
> arch/x86/kvm/lapic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 3242f3da2457..0959a887c306 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2768,7 +2768,7 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
> trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
>
> r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
> - if (r && lvt_type == APIC_LVTPC)
> + if (r && lvt_type == APIC_LVTPC && !guest_cpuid_is_amd_or_hygon(apic->vcpu))
Perhaps we could use a positive predicate instead:
guest_cpuid_is_intel(apic->vcpu)?
> kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);
> return r;
> }
> --
> 2.34.1
Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
