Re: [RFC PATCH v5 15/29] KVM: selftests: TDX: Add TDX MSR read/write tests

[Binbin Wu <binbin.wu@xxxxxxxxxxxxxxx>]

On 3/1/2024 8:00 PM, Binbin Wu wrote:
> On 12/13/2023 4:46 AM, Sagi Shahar wrote:
> > The test verifies reads and writes for MSR registers with different 
> > access
> > level.
> >
> > Signed-off-by: Sagi Shahar <sagis@xxxxxxxxxx>
> > Signed-off-by: Ackerley Tng <ackerleytng@xxxxxxxxxx>
> > Signed-off-by: Ryan Afranji <afranji@xxxxxxxxxx>
> > ---
> >   .../selftests/kvm/include/x86_64/tdx/tdx.h    |   5 +
> >   .../selftests/kvm/lib/x86_64/tdx/tdx.c        |  27 +++
> >   .../selftests/kvm/x86_64/tdx_vm_tests.c       | 209 ++++++++++++++++++
> >   3 files changed, 241 insertions(+)
> >
> > diff --git a/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h 
> > b/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h
> > index 63788012bf94..85ba6aab79a7 100644
> > --- a/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h
> > +++ b/tools/testing/selftests/kvm/include/x86_64/tdx/tdx.h
> > @@ -9,11 +9,16 @@
> >   #define TDG_VP_VMCALL_REPORT_FATAL_ERROR 0x10003
> >     #define TDG_VP_VMCALL_INSTRUCTION_IO 30
> > +#define TDG_VP_VMCALL_INSTRUCTION_RDMSR 31
> > +#define TDG_VP_VMCALL_INSTRUCTION_WRMSR 32
> > +
> >   void handle_userspace_tdg_vp_vmcall_exit(struct kvm_vcpu *vcpu);
> >   uint64_t tdg_vp_vmcall_instruction_io(uint64_t port, uint64_t size,
> >                         uint64_t write, uint64_t *data);
> >   void tdg_vp_vmcall_report_fatal_error(uint64_t error_code, uint64_t 
> > data_gpa);
> >   uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t *r11, uint64_t 
> > *r12,
> >                       uint64_t *r13, uint64_t *r14);
> > +uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t 
> > *ret_value);
> > +uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t 
> > value);
> >     #endif // SELFTEST_TDX_TDX_H
> > diff --git a/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c 
> > b/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c
> > index e5a9e13c62e2..88ea6f2a6469 100644
> > --- a/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c
> > +++ b/tools/testing/selftests/kvm/lib/x86_64/tdx/tdx.c
> > @@ -87,3 +87,30 @@ uint64_t tdg_vp_vmcall_get_td_vmcall_info(uint64_t 
> > *r11, uint64_t *r12,
> >         return ret;
> >   }
> > +
> > +uint64_t tdg_vp_vmcall_instruction_rdmsr(uint64_t index, uint64_t 
> > *ret_value)
> > +{
> > +    uint64_t ret;
> > +    struct tdx_hypercall_args args = {
> > +        .r11 = TDG_VP_VMCALL_INSTRUCTION_RDMSR,
> > +        .r12 = index,
> > +    };
> > +
> > +    ret = __tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT);
> > +
> > +    if (ret_value)
> > +        *ret_value = args.r11;
> > +
> > +    return ret;
> > +}
> > +
> > +uint64_t tdg_vp_vmcall_instruction_wrmsr(uint64_t index, uint64_t 
> > value)
> > +{
> > +    struct tdx_hypercall_args args = {
> > +        .r11 = TDG_VP_VMCALL_INSTRUCTION_WRMSR,
> > +        .r12 = index,
> > +        .r13 = value,
> > +    };
> > +
> > +    return __tdx_hypercall(&args, 0);
> > +}
> > diff --git a/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c 
> > b/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c
> > index 699cba36e9ce..5db3701cc6d9 100644
> > --- a/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c
> > +++ b/tools/testing/selftests/kvm/x86_64/tdx_vm_tests.c
> > @@ -515,6 +515,213 @@ void verify_guest_reads(void)
> >       printf("\t ... PASSED\n");
> >   }
> >   +/*
> > + * Define a filter which denies all MSR access except the following:
> > + * MSR_X2APIC_APIC_ICR: Allow read/write access (allowed by default)
>
> The default filtering behavior of tdx_msr_test_filter is
> KVM_MSR_FILTER_DEFAULT_DENY, and MSR_X2APIC_APIC_ICR is not covered
> by any specific range, shouldn't MSR_X2APIC_APIC_ICR be denied by 
> default?

Sorry, please ignore this comment.

I see the description from the KVM document later:
"x2APIC MSR accesses cannot be filtered (KVM silently ignores filters 
that cover any x2APIC MSRs)."

> > + * MSR_IA32_MISC_ENABLE: Allow read access
> > + * MSR_IA32_POWER_CTL: Allow write access
> > + */
> > +#define MSR_X2APIC_APIC_ICR 0x830
> > +static u64 tdx_msr_test_allow_bits = 0xFFFFFFFFFFFFFFFF;
> > +struct kvm_msr_filter tdx_msr_test_filter = {
> > +    .flags = KVM_MSR_FILTER_DEFAULT_DENY,
> > +    .ranges = {
> > +        {
> > +            .flags = KVM_MSR_FILTER_READ,
> > +            .nmsrs = 1,
> > +            .base = MSR_IA32_MISC_ENABLE,
> > +            .bitmap = (uint8_t *)&tdx_msr_test_allow_bits,
> > +        }, {
> > +            .flags = KVM_MSR_FILTER_WRITE,
> > +            .nmsrs = 1,
> > +            .base = MSR_IA32_POWER_CTL,
> > +            .bitmap = (uint8_t *)&tdx_msr_test_allow_bits,
> > +        },
> > +    },
> > +};
> > +
> > +/*
> > + * Verifies MSR read functionality.
> > + */
> > +void guest_msr_read(void)
> > +{
> > +    uint64_t data;
> > +    uint64_t ret;
> > +
> > +    ret = tdg_vp_vmcall_instruction_rdmsr(MSR_X2APIC_APIC_ICR, &data);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    ret = tdx_test_report_64bit_to_user_space(data);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    ret = tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_MISC_ENABLE, &data);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    ret = tdx_test_report_64bit_to_user_space(data);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    /* We expect this call to fail since MSR_IA32_POWER_CTL is write 
> > only */
> > +    ret = tdg_vp_vmcall_instruction_rdmsr(MSR_IA32_POWER_CTL, &data);
> > +    if (ret) {
> > +        ret = tdx_test_report_64bit_to_user_space(ret);
> > +        if (ret)
> > +            tdx_test_fatal(ret);
> > +    } else {
> > +        tdx_test_fatal(-99);
> > +    }
> > +
> > +    tdx_test_success();
> > +}
> > +
> > +void verify_guest_msr_reads(void)
> > +{
> > +    struct kvm_vm *vm;
> > +    struct kvm_vcpu *vcpu;
> > +
> > +    uint64_t data;
> > +    int ret;
> > +
> > +    vm = td_create();
> > +    td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0);
> > +
> > +    /*
> > +     * Set explicit MSR filter map to control access to the MSR 
> > registers
> > +     * used in the test.
> > +     */
> > +    printf("\t ... Setting test MSR filter\n");
> > +    ret = kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR);
> > +    TEST_ASSERT(ret, "KVM_CAP_X86_USER_SPACE_MSR is unavailable");
> > +    vm_enable_cap(vm, KVM_CAP_X86_USER_SPACE_MSR, 
> > KVM_MSR_EXIT_REASON_FILTER);
> > +
> > +    ret = kvm_check_cap(KVM_CAP_X86_MSR_FILTER);
> > +    TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable");
> > +
> > +    ret = ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter);
> > +    TEST_ASSERT(ret == 0,
> > +            "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)",
> > +            ret, errno, strerror(errno));
> > +
> > +    vcpu = td_vcpu_add(vm, 0, guest_msr_read);
> > +    td_finalize(vm);
> > +
> > +    printf("Verifying guest msr reads:\n");
> > +
> > +    printf("\t ... Setting test MSR values\n");
> > +    /* Write arbitrary to the MSRs. */
> > +    vcpu_set_msr(vcpu, MSR_X2APIC_APIC_ICR, 4);
> > +    vcpu_set_msr(vcpu, MSR_IA32_MISC_ENABLE, 5);
> > +    vcpu_set_msr(vcpu, MSR_IA32_POWER_CTL, 6);
> > +
> > +    printf("\t ... Running guest\n");
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_CHECK_GUEST_FAILURE(vcpu);
> > +    data = tdx_test_read_64bit_report_from_guest(vcpu);
> > +    TEST_ASSERT_EQ(data, 4);
> > +
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_CHECK_GUEST_FAILURE(vcpu);
> > +    data = tdx_test_read_64bit_report_from_guest(vcpu);
> > +    TEST_ASSERT_EQ(data, 5);
> > +
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_CHECK_GUEST_FAILURE(vcpu);
> > +    data = tdx_test_read_64bit_report_from_guest(vcpu);
> > +    TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND);
> > +
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_ASSERT_SUCCESS(vcpu);
> > +
> > +    kvm_vm_free(vm);
> > +    printf("\t ... PASSED\n");
> > +}
> > +
> > +/*
> > + * Verifies MSR write functionality.
> > + */
> > +void guest_msr_write(void)
> > +{
> > +    uint64_t ret;
> > +
> > +    ret = tdg_vp_vmcall_instruction_wrmsr(MSR_X2APIC_APIC_ICR, 4);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    /* We expect this call to fail since MSR_IA32_MISC_ENABLE is 
> > read only */
> > +    ret = tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_MISC_ENABLE, 5);
> > +    if (ret) {
> > +        ret = tdx_test_report_64bit_to_user_space(ret);
> > +        if (ret)
> > +            tdx_test_fatal(ret);
> > +    } else {
> > +        tdx_test_fatal(-99);
> > +    }
> > +
> > +
> > +    ret = tdg_vp_vmcall_instruction_wrmsr(MSR_IA32_POWER_CTL, 6);
> > +    if (ret)
> > +        tdx_test_fatal(ret);
> > +
> > +    tdx_test_success();
> > +}
> > +
> > +void verify_guest_msr_writes(void)
> > +{
> > +    struct kvm_vcpu *vcpu;
> > +    struct kvm_vm *vm;
> > +
> > +    uint64_t data;
> > +    int ret;
> > +
> > +    vm = td_create();
> > +    td_initialize(vm, VM_MEM_SRC_ANONYMOUS, 0);
> > +
> > +    /*
> > +     * Set explicit MSR filter map to control access to the MSR 
> > registers
> > +     * used in the test.
> > +     */
> > +    printf("\t ... Setting test MSR filter\n");
> > +    ret = kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR);
> > +    TEST_ASSERT(ret, "KVM_CAP_X86_USER_SPACE_MSR is unavailable");
> > +    vm_enable_cap(vm, KVM_CAP_X86_USER_SPACE_MSR, 
> > KVM_MSR_EXIT_REASON_FILTER);
> > +
> > +    ret = kvm_check_cap(KVM_CAP_X86_MSR_FILTER);
> > +    TEST_ASSERT(ret, "KVM_CAP_X86_MSR_FILTER is unavailable");
> > +
> > +    ret = ioctl(vm->fd, KVM_X86_SET_MSR_FILTER, &tdx_msr_test_filter);
> > +    TEST_ASSERT(ret == 0,
> > +            "KVM_X86_SET_MSR_FILTER failed, ret: %i errno: %i (%s)",
> > +            ret, errno, strerror(errno));
> > +
> > +    vcpu = td_vcpu_add(vm, 0, guest_msr_write);
> > +    td_finalize(vm);
> > +
> > +    printf("Verifying guest msr writes:\n");
> > +
> > +    printf("\t ... Running guest\n");
> > +    /* Only the write to MSR_IA32_MISC_ENABLE should trigger an exit */
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_CHECK_GUEST_FAILURE(vcpu);
> > +    data = tdx_test_read_64bit_report_from_guest(vcpu);
> > +    TEST_ASSERT_EQ(data, TDG_VP_VMCALL_INVALID_OPERAND);
> > +
> > +    td_vcpu_run(vcpu);
> > +    TDX_TEST_ASSERT_SUCCESS(vcpu);
> > +
> > +    printf("\t ... Verifying MSR values writen by guest\n");
> > +
> > +    TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_X2APIC_APIC_ICR), 4);
> > +    TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_MISC_ENABLE), 0x1800);
> > +    TEST_ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_POWER_CTL), 6);
> > +
> > +    kvm_vm_free(vm);
> > +    printf("\t ... PASSED\n");
> > +}
> > +
> > +
> >   int main(int argc, char **argv)
> >   {
> >       setbuf(stdout, NULL);
> > @@ -531,6 +738,8 @@ int main(int argc, char **argv)
> >       run_in_new_process(&verify_get_td_vmcall_info);
> >       run_in_new_process(&verify_guest_writes);
> >       run_in_new_process(&verify_guest_reads);
> > +    run_in_new_process(&verify_guest_msr_writes);
> > +    run_in_new_process(&verify_guest_msr_reads);
> >         return 0;
> >   }