Add description for the Ssccfg extension.
Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
---
.../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 77a9f867e36b..15adeb60441b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,13 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smcdeleg
+ description: |
+ The standard Smcdeleg supervisor-level extension for the machine mode
+ to delegate the hpmcounters to supvervisor mode so that they are
+ directlyi accessible in the supervisor mode. This extension depend
+ on Sscsrind, Zihpm, Zicntr extensions.
+
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
@@ -154,6 +161,12 @@ properties:
interrupt architecture for supervisor-mode-visible csr and
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: ssccfg
+ description: |
+ The standard Ssccfg supervisor-level extension for configuring
+ the delegated hpmcounters to be accessible directly in supervisor
+ mode. This extension depend on Sscsrind, Smcdeleg, Zihpm, Zicntr
+ extensions.
- const: sscofpmf
description: |
--
2.34.1
