Add the S[m|s]csrind ISA extension description.
Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
---
.../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895e5..77a9f867e36b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -134,6 +134,20 @@ properties:
added by other RISC-V extensions in H/S/VS/U/VU modes and as
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+ - const: smcsrind
+ description: |
+ The standard Smcsrind supervisor-level extension extends the
+ indirect CSR access mechanism defined by the Smaia extension. This
+ extension allows other ISA extension to use indirect CSR access
+ mechanism in M-mode.
+
+ - const: sscsrind
+ description: |
+ The standard Sscsrind supervisor-level extension extends the
+ indirect CSR access mechanism defined by the Ssaia extension. This
+ extension allows other ISA extension to use indirect CSR access
+ mechanism in S-mode.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
--
2.34.1
