AMD SNP guests may have Secure TSC feature enabled. Use the Secure TSC as the only reliable clock source in SEV-SNP guests when enabled, bypassing unstable calibration. Signed-off-by: Nikunj A Dadhania <nikunj@xxxxxxx> Tested-by: Peter Gonda <pgonda@xxxxxxxxxx> --- arch/x86/mm/mem_encrypt_amd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index c81b57ca03b6..cc936999efc8 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -498,6 +498,10 @@ void __init sme_early_init(void) */ if (sev_status & MSR_AMD64_SEV_ENABLED) ia32_disable(); + + /* Mark the TSC as reliable when Secure TSC is enabled */ + if (sev_status & MSR_AMD64_SNP_SECURE_TSC) + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); } void __init mem_encrypt_free_decrypted_mem(void) -- 2.34.1
