From: Zhao Liu <zhao1.liu@xxxxxxxxx>
Add the definition of more bits of these MSRs:
* MSR_IA32_THERM_CONTROL
* MSR_IA32_THERM_INTERRUPT
* MSR_IA32_THERM_STATUS
* MSR_IA32_PACKAGE_THERM_STATUS
* MSR_IA32_PACKAGE_THERM_INTERRUPT
The virtualization of thermal events need these extra definitions.
While here, regroup the definitions and use the BIT_ULL() and
GENMASK_ULL() macro to improve readability.
Tested-by: Yanting Jiang <yanting.jiang@xxxxxxxxx>
Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
---
arch/x86/include/asm/msr-index.h | 54 +++++++++++++++++++----------
drivers/thermal/intel/therm_throt.c | 1 -
2 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 65b1bfb9c304..4f7ebfafa46a 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -829,17 +829,26 @@
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
-#define MSR_IA32_THERM_CONTROL 0x0000019a
-#define MSR_IA32_THERM_INTERRUPT 0x0000019b
-
-#define THERM_INT_HIGH_ENABLE (1 << 0)
-#define THERM_INT_LOW_ENABLE (1 << 1)
-#define THERM_INT_PLN_ENABLE (1 << 24)
-
-#define MSR_IA32_THERM_STATUS 0x0000019c
+#define MSR_IA32_THERM_CONTROL 0x0000019a
+#define THERM_ON_DEM_CLO_MOD_DUTY_CYC_MASK GENMASK_ULL(3, 1)
+#define THERM_ON_DEM_CLO_MOD_ENABLE BIT_ULL(4)
-#define THERM_STATUS_PROCHOT (1 << 0)
-#define THERM_STATUS_POWER_LIMIT (1 << 10)
+#define MSR_IA32_THERM_INTERRUPT 0x0000019b
+#define THERM_INT_HIGH_ENABLE BIT_ULL(0)
+#define THERM_INT_LOW_ENABLE BIT_ULL(1)
+#define THERM_INT_PROCHOT_ENABLE BIT_ULL(2)
+#define THERM_INT_FORCEPR_ENABLE BIT_ULL(3)
+#define THERM_INT_CRITICAL_TEM_ENABLE BIT_ULL(4)
+#define THERM_INT_PLN_ENABLE BIT_ULL(24)
+
+#define MSR_IA32_THERM_STATUS 0x0000019c
+#define THERM_STATUS_PROCHOT BIT_ULL(0)
+#define THERM_STATUS_PROCHOT_LOG BIT_ULL(1)
+#define THERM_STATUS_PROCHOT_FORCEPR_EVENT BIT_ULL(2)
+#define THERM_STATUS_PROCHOT_FORCEPR_LOG BIT_ULL(3)
+#define THERM_STATUS_CRITICAL_TEMP BIT_ULL(4)
+#define THERM_STATUS_CRITICAL_TEMP_LOG BIT_ULL(5)
+#define THERM_STATUS_POWER_LIMIT BIT_ULL(10)
#define MSR_THERM2_CTL 0x0000019d
@@ -861,17 +870,24 @@
#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
-
-#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
-#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
-#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
+#define PACKAGE_THERM_STATUS_PROCHOT BIT_ULL(0)
+#define PACKAGE_THERM_STATUS_PROCHOT_LOG BIT_ULL(1)
+#define PACKAGE_THERM_STATUS_PROCHOT_EVENT BIT_ULL(2)
+#define PACKAGE_THERM_STATUS_PROCHOT_EVENT_LOG BIT_ULL(3)
+#define PACKAGE_THERM_STATUS_CRITICAL_TEMP BIT_ULL(4)
+#define PACKAGE_THERM_STATUS_CRITICAL_TEMP_LOG BIT_ULL(5)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT BIT_ULL(10)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT_LOG BIT_ULL(11)
+#define PACKAGE_THERM_STATUS_DIG_READOUT_MASK GENMASK_ULL(22, 16)
+#define PACKAGE_THERM_STATUS_HFI_UPDATED BIT_ULL(26)
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
-
-#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
-#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
-#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
-#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
+#define PACKAGE_THERM_INT_HIGH_ENABLE BIT_ULL(0)
+#define PACKAGE_THERM_INT_LOW_ENABLE BIT_ULL(1)
+#define PACKAGE_THERM_INT_PROCHOT_ENABLE BIT_ULL(2)
+#define PACKAGE_THERM_INT_OVERHEAT_ENABLE BIT_ULL(4)
+#define PACKAGE_THERM_INT_PLN_ENABLE BIT_ULL(24)
+#define PACKAGE_THERM_INT_HFI_ENABLE BIT_ULL(25)
/* Thermal Thresholds Support */
#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index e69868e868eb..4c72fee32bf2 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -191,7 +191,6 @@ static const struct attribute_group thermal_attr_group = {
#endif /* CONFIG_SYSFS */
#define THERM_THROT_POLL_INTERVAL HZ
-#define THERM_STATUS_PROCHOT_LOG BIT(1)
static u64 therm_intr_core_clear_mask;
static u64 therm_intr_pkg_clear_mask;
--
2.34.1
