On Thu, Dec 21, 2023 at 09:02:35AM -0500, Yang Weijiang wrote: > Enable/disable CET MSRs interception per associated feature configuration. > Shadow Stack feature requires all CET MSRs passed through to guest to make > it supported in user and supervisor mode while IBT feature only depends on > MSR_IA32_{U,S}_CETS_CET to enable user and supervisor IBT. > > Note, this MSR design introduced an architectural limitation of SHSTK and > IBT control for guest, i.e., when SHSTK is exposed, IBT is also available > to guest from architectual perspective since IBT relies on subset of SHSTK > relevant MSRs. > > Signed-off-by: Yang Weijiang <weijiang.yang@xxxxxxxxx> > --- > arch/x86/kvm/vmx/vmx.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 064a5fe87948..08058b182893 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -692,6 +692,10 @@ static bool is_valid_passthrough_msr(u32 msr) > case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: > /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ > return true; > + case MSR_IA32_U_CET: > + case MSR_IA32_S_CET: > + case MSR_IA32_PL0_SSP ... MSR_IA32_INT_SSP_TAB: > + return true; > } > > r = possible_passthrough_msr_slot(msr) != -ENOENT; > @@ -7767,6 +7771,42 @@ static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) > vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); > } > > +static void vmx_update_intercept_for_cet_msr(struct kvm_vcpu *vcpu) > +{ > + bool incpt; > + > + if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { > + incpt = !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK); > + > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, > + MSR_TYPE_RW, incpt); > + if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) Looks this leading to MSR_IA32_INT_SSP_TAB not intercepted after below steps: Step 1. User space set cpuid w/ X86_FEATURE_LM, w/ SHSTK. Step 2. User space set cpuid w/o X86_FEATURE_LM, w/o SHSTK. Then MSR_IA32_INT_SSP_TAB won't be intercepted even w/o SHSTK on guest cpuid, will this lead to inconsistency when do rdmsr(MSR_IA32_INT_SSP_TAB) from guest in this scenario ? > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_INT_SSP_TAB, > + MSR_TYPE_RW, incpt); > + if (!incpt) > + return; > + } > + > + if (kvm_cpu_cap_has(X86_FEATURE_IBT)) { > + incpt = !guest_cpuid_has(vcpu, X86_FEATURE_IBT); > + > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, > + MSR_TYPE_RW, incpt); > + vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, > + MSR_TYPE_RW, incpt); > + } > +} > + > static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) > { > struct vcpu_vmx *vmx = to_vmx(vcpu); > @@ -7845,6 +7885,8 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) > > /* Refresh #PF interception to account for MAXPHYADDR changes. */ > vmx_update_exception_bitmap(vcpu); > + > + vmx_update_intercept_for_cet_msr(vcpu); > } > > static u64 vmx_get_perf_capabilities(void) > -- > 2.39.3 > >