On Thu, Jan 4, 2024 at 5:04 AM Alex Bennée <alex.bennee@xxxxxxxxxx> wrote:
>
> From: Akihiko Odaki <akihiko.odaki@xxxxxxxxxx>
>
> misa_mxl_max is now a class member and initialized only once for each
> class. This also moves the initialization of gdb_core_xml_file which
> will be referenced before realization in the future.
>
> Signed-off-by: Akihiko Odaki <akihiko.odaki@xxxxxxxxxx>
> Message-Id: <20231213-riscv-v7-4-a760156a337f@xxxxxxxxxx>
> Signed-off-by: Alex Bennée <alex.bennee@xxxxxxxxxx>
Acked-by: Alistair Francis <alistair.francis@xxxxxxx>
Alistair
> ---
> target/riscv/cpu.c | 21 +++++++++++++++++++++
> target/riscv/tcg/tcg-cpu.c | 23 -----------------------
> 2 files changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2ab61df2217..b799f133604 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1247,6 +1247,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {
> MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
> };
>
> +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
> +{
> + CPUClass *cc = CPU_CLASS(mcc);
> +
> + /* Validate that MISA_MXL is set properly. */
> + switch (mcc->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + case MXL_RV128:
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> + break;
> +#endif
> + case MXL_RV32:
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> static int riscv_validate_misa_info_idx(uint32_t bit)
> {
> int idx;
> @@ -1695,6 +1715,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>
> mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
> + riscv_cpu_validate_misa_mxl(mcc);
> }
>
> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 7f6712c81a4..eb243e011ca 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> }
> }
>
> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
> -{
> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> - CPUClass *cc = CPU_CLASS(mcc);
> -
> - /* Validate that MISA_MXL is set properly. */
> - switch (mcc->misa_mxl_max) {
> -#ifdef TARGET_RISCV64
> - case MXL_RV64:
> - case MXL_RV128:
> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> - break;
> -#endif
> - case MXL_RV32:
> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> - break;
> - default:
> - g_assert_not_reached();
> - }
> -}
> -
> static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> {
> CPURISCVState *env = &cpu->env;
> @@ -676,8 +655,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
> return false;
> }
>
> - riscv_cpu_validate_misa_mxl(cpu);
> -
> #ifndef CONFIG_USER_ONLY
> CPURISCVState *env = &cpu->env;
> Error *local_err = NULL;
> --
> 2.39.2
>
>
