From: Zhao Liu <zhao1.liu@xxxxxxxxx>
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x80000026]) have the different definitions with different
enumeration values.
Though CPUID[0x80000026] hasn't been implemented in QEMU, to avoid
possible misunderstanding, split topology types of CPUID[0x1F] from the
definitions of CPUID[0xB] and introduce CPUID[0x1F]-specific topology
types.
Signed-off-by: Zhao Liu <zhao1.liu@xxxxxxxxx>
Tested-by: Babu Moger <babu.moger@xxxxxxx>
Tested-by: Yongwei Ma <yongwei.ma@xxxxxxxxx>
Acked-by: Michael S. Tsirkin <mst@xxxxxxxxxx>
---
Changes since v3:
* New commit to prepare to refactor CPUID[0x1F] encoding.
---
target/i386/cpu.c | 14 +++++++-------
target/i386/cpu.h | 13 +++++++++----
2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6f8fa772ecf8..bc440477d13d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6255,17 +6255,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
case 0:
*eax = apicid_core_offset(&topo_info);
*ebx = topo_info.threads_per_core;
- *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
+ *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8;
break;
case 1:
*eax = apicid_pkg_offset(&topo_info);
*ebx = cpus_per_pkg;
- *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
+ *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8;
break;
default:
*eax = 0;
*ebx = 0;
- *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
+ *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8;
}
assert(!(*eax & ~0x1f));
@@ -6290,22 +6290,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
case 0:
*eax = apicid_core_offset(&topo_info);
*ebx = topo_info.threads_per_core;
- *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
+ *ecx |= CPUID_1F_ECX_TOPO_LEVEL_SMT << 8;
break;
case 1:
*eax = apicid_die_offset(&topo_info);
*ebx = topo_info.cores_per_die * topo_info.threads_per_core;
- *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
+ *ecx |= CPUID_1F_ECX_TOPO_LEVEL_CORE << 8;
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
*ebx = cpus_per_pkg;
- *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
+ *ecx |= CPUID_1F_ECX_TOPO_LEVEL_DIE << 8;
break;
default:
*eax = 0;
*ebx = 0;
- *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
+ *ecx |= CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8;
}
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index ef987f344cff..f47bad46db5e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1009,10 +1009,15 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
/* CPUID[0xB].ECX level types */
-#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
-#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
-#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
-#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
+#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
+#define CPUID_B_ECX_TOPO_LEVEL_SMT 1
+#define CPUID_B_ECX_TOPO_LEVEL_CORE 2
+
+/* COUID[0x1F].ECX level types */
+#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID
+#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT
+#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE
+#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5
/* MSR Feature Bits */
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
--
2.34.1
