> From: Liu, Yi L <yi.l.liu@xxxxxxxxx> > Sent: Thursday, December 28, 2023 12:14 AM > +/** > + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation > + * (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) > + * @addr: The start address of the range to be invalidated. It needs to > + * be 4KB aligned. > + * @npages: Number of contiguous 4K pages to be invalidated. > + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags > + * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error > + * > + * The Intel VT-d specific invalidation data for user-managed stage-1 cache > + * invalidation in nested translation. Userspace uses this structure to > + * tell the impacted cache scope after modifying the stage-1 page table. > + * > + * Invalidating all the caches related to the page table by setting @addr > + * to be 0 and @npages to be U64_MAX. > + * > + * The device TLB will be invalidated automatically if ATS is enabled. > + * > + * The @hw_error is meaningful when the entry is handled by the kernel. > + * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to > know the > + * handled entries. @hw_error only covers the errors detected by hardware. > + * The software detected errors would go through the normal ioctl errno. > + */ * An entry is considered 'handled' after it passes the audit and submitted * to the IOMMU by the underlying driver. Check the @entry_num output of * struct iommu_hwpt_invalidate for the number of handled entries. A 'handled' * request may still fail in hardware for various reasons, e.g. due to timeout * on waiting for device response upon a device TLB invalidation request. In * such case the hardware error info is reported in the @hw_error field of the * handled entry.
