On Sat, Nov 11 2023 at 20:16, Jacob Pan wrote:
> + /*
> + * Ideally, we should start from the high order bits set in the PIR
> + * since each bit represents a vector. Higher order bit position means
> + * the vector has higher priority. But external vectors are allocated
> + * based on availability not priority.
> + *
> + * EOI is included in the IRQ handlers call to apic_ack_irq, which
> + * allows higher priority system interrupt to get in between.
What? This does not make sense.
_IF_ we go there then
1) The EOI must be explicit in sysvec_posted_msi_notification()
2) Interrupt enabling must happen explicit at a dedicated place in
sysvec_posted_msi_notification()
You _CANNOT_ run all the device handlers with interrupts
enabled.
Please remove all traces of non-working wishful thinking from this series.
> + */
> + for_each_set_bit_from(vec, (unsigned long *)&pir_copy[0], 256)
Why does this need to check up to vector 255? The vector space does not
magially expand just because of posted interrupts, really. At least not
without major modifications to the vector management.
> + call_irq_handler(vec, regs);
> +
Stray newline.
> +}
Thanks,
tglx
