On Tue, Oct 24, 2023 at 01:08:14AM -0700, Pawan Gupta wrote: > Legacy instruction VERW was overloaded by some processors to clear Can you raise a bug against the SDM? The VERR/VERW instruction is out-of-order alphabetically; my copy of Volume 2 from June 2023 has it placed between VEXPANDPS and VEXTRACTF128.
