When running pmu test on Intel Sapphire Rapids, we found several failures are encountered, such as "llc misses" failure, "all counters" failure and "fixed counter 3" failure. Intel Sapphire Rapids introduces new fixed counter 3, total PMU counters including GP and fixed counters increase to 12 and also optimizes cache subsystem. All these changes make the original assumptions in pmu test unavailable any more on Sapphire Rapids. Patches 2-4 fixes these failures, patch 0 remove the duplicate code and patch 5 adds assert to ensure predefine fixed events are matched with HW fixed counters. Dapeng Mi (4): x86: pmu: Change the minimum value of llc_misses event to 0 x86: pmu: Enlarge cnt array length to 64 in check_counters_many() x86: pmu: Support validation for Intel PMU fixed counter 3 x86: pmu: Add asserts to warn inconsistent fixed events and counters Xiong Zhang (1): x86: pmu: Remove duplicate code in pmu_init() lib/x86/pmu.c | 5 ----- x86/pmu.c | 17 ++++++++++++----- 2 files changed, 12 insertions(+), 10 deletions(-) base-commit: bfe5d7d0e14c8199d134df84d6ae8487a9772c48 -- 2.34.1
