PMU event exception level filtering fixes Fixes to KVM's handling of the PMUv3 exception level filtering bits: - NSH (count at EL2) and M (count at EL3) should be stateful when the respective EL is advertised in the ID registers but have no effect on event counting. - NSU and NSK modify the event filtering of EL0 and EL1, respectively. Though the kernel may not use these bits, other KVM guests might. Implement these bits exactly as written in the pseudocode if EL3 is advertised. v2: https://lore.kernel.org/kvmarm/20231013052901.170138-1-oliver.upton@xxxxxxxxx/ v2 -> v3: - Make the bits conditional on the ID register values - Allow the guest to set the M and NSH bits without effect (Marc) Oliver Upton (2): KVM: arm64: Make PMEVTYPER<n>_EL0.NSH RES0 if EL2 isn't advertised KVM: arm64: Add PMU event filter bits required if EL3 is implemented arch/arm64/kvm/pmu-emul.c | 36 +++++++++++++++++++++++++--------- arch/arm64/kvm/sys_regs.c | 8 ++++++-- include/kvm/arm_pmu.h | 5 +++++ include/linux/perf/arm_pmuv3.h | 9 ++++++--- 4 files changed, 44 insertions(+), 14 deletions(-) base-commit: 6465e260f48790807eef06b583b38ca9789b6072 -- 2.42.0.655.g421f12c284-goog
