On 19/10/2023 10:14, Joao Martins wrote:
> On 19/10/2023 04:04, Baolu Lu wrote:
>> On 10/19/23 4:27 AM, Joao Martins wrote:
>>> +/*
>>> + * Enable second level A/D bits by setting the SLADE (Second Level
>>
>> nit: Disable second level ....
>>
> /me nods
>
>>> + * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
>>> + * entry.
>>> + */
>>> +static inline void pasid_clear_ssade(struct pasid_entry *pe)
>>> +{
>>> + pasid_set_bits(&pe->val[0], 1 << 9, 0);
>>> +}
>>> +
>>> +/*
>>> + * Checks if second level A/D bits by setting the SLADE (Second Level
>>> + * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
>>> + * entry is enabled.
>>> + */
>>> +static inline bool pasid_get_ssade(struct pasid_entry *pe)
>>> +{
>>> + return pasid_get_bits(&pe->val[0]) & (1 << 9);
>>> +}
>>> +
Adjusted this part a little better:
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 785384a59d55..deb775d84499 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -351,7 +351,7 @@ static inline void pasid_set_ssade(struct pasid_entry *pe)
}
/*
- * Enable second level A/D bits by setting the SLADE (Second Level
+ * Disable second level A/D bits by clearing the SLADE (Second Level
* Access Dirty Enable) field (Bit 9) of a scalable mode PASID
* entry.
*/
@@ -361,9 +361,9 @@ static inline void pasid_clear_ssade(struct pasid_entry *pe)
}
/*
- * Checks if second level A/D bits by setting the SLADE (Second Level
+ * Checks if second level A/D bits specifically the SLADE (Second Level
* Access Dirty Enable) field (Bit 9) of a scalable mode PASID
- * entry is enabled.
+ * entry is set.
*/
static inline bool pasid_get_ssade(struct pasid_entry *pe)
{
