On 10/17/2023 11:47 PM, John Allen wrote:
> On Thu, Oct 12, 2023 at 02:31:19PM +0530, Nikunj A. Dadhania wrote:
>> On 10/11/2023 1:32 AM, John Allen wrote:
>>> If kvm supports shadow stack, pass through shadow stack MSRs to improve
>>> guest performance.
>>>
>>> Signed-off-by: John Allen <john.allen@xxxxxxx>
>>> ---
>>> arch/x86/kvm/svm/svm.c | 26 ++++++++++++++++++++++++++
>>> arch/x86/kvm/svm/svm.h | 2 +-
>>> 2 files changed, 27 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
>>> index e435e4fbadda..984e89d7a734 100644
>>> --- a/arch/x86/kvm/svm/svm.c
>>> +++ b/arch/x86/kvm/svm/svm.c
>>> @@ -139,6 +139,13 @@ static const struct svm_direct_access_msrs {
>>> { .index = X2APIC_MSR(APIC_TMICT), .always = false },
>>> { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
>>> { .index = X2APIC_MSR(APIC_TDCR), .always = false },
>>> + { .index = MSR_IA32_U_CET, .always = false },
>>> + { .index = MSR_IA32_S_CET, .always = false },
>>> + { .index = MSR_IA32_INT_SSP_TAB, .always = false },
>>> + { .index = MSR_IA32_PL0_SSP, .always = false },
>>> + { .index = MSR_IA32_PL1_SSP, .always = false },
>>> + { .index = MSR_IA32_PL2_SSP, .always = false },
>>> + { .index = MSR_IA32_PL3_SSP, .always = false },
>>
>> First three MSRs are emulated in the patch 1, any specific reason for skipping MSR_IA32_PL[0-3]_SSP ?
>
> I'm not sure what you mean.
MSR_IA32_U_CET, MSR_IA32_S_CET and MSR_IA32_INT_SSP_TAB are selectively emulated and there is no good explanation why MSR_IA32_PL[0-3]_SSP do not need emulation. Moreover, MSR interception is initially set (i.e. always=false) for MSR_IA32_PL[0-3]_SSP.
> The PLx_SSP MSRS should be getting passed
> through here unless I'm misunderstanding something.
In that case, intercept should be cleared from the very beginning.
+ { .index = MSR_IA32_PL0_SSP, .always = true },
+ { .index = MSR_IA32_PL1_SSP, .always = true },
+ { .index = MSR_IA32_PL2_SSP, .always = true },
+ { .index = MSR_IA32_PL3_SSP, .always = true },
Regards
Nikunj
