Re: [PATCH v3 19/19] iommu/intel: Access/Dirty bit support for SL domains

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On 2023/10/16 19:39, Joao Martins wrote:
+    /* Device IOTLB doesn't need to be flushed in caching mode. */
+    if (!cap_caching_mode(iommu->cap))
+        devtlb_invalidation_with_pasid(iommu, dev, pasid);
For the device IOTLB invalidation, need to follow what spec requires.

   If (pasid is RID_PASID)
    - Global Device-TLB invalidation to affected functions
   Else
    - PASID-based Device-TLB invalidation (with S=1 and
      Addr[63:12]=0x7FFFFFFF_FFFFF) to affected functions

devtlb_invalidation_with_pasid() underneath does:

	if (pasid == PASID_RID2PASID)
		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
	else
		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT);

... Which is what the spec suggests (IIUC).

Ah! I overlooked this. Sorry about it.

Should I read your comment above as to drop the cap_caching_mode(iommu->cap) ?

No. Your code is fine.

Best regards,
baolu



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