Clear mask in PMI handler to allow subsequent PMI delivered. SDM 11.5.1
Local Vector Table mentions: "When the local APIC handles a
performance-monitoring counters interrupt, it automatically sets the mask
flag in the LVT performance counter register. This flag is set to 1 on
reset. It can be cleared only by software."
Previously KVM vPMU does not set the mask when injecting the PMI, so there
is no issue for this test to work correctly. To ensure the test still works
after the KVM fix merges, add the mask clearing behavior to PMI handler.
Signed-off-by: Mingwei Zhang <mizhang@xxxxxxxxxx>
---
x86/pmu.c | 1 +
x86/pmu_pebs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/x86/pmu.c b/x86/pmu.c
index 0def2869..667e6233 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -68,6 +68,7 @@ volatile uint64_t irq_received;
static void cnt_overflow(isr_regs_t *regs)
{
irq_received++;
+ apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
apic_write(APIC_EOI, 0);
}
diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c
index d1a68ca3..ff943f0e 100644
--- a/x86/pmu_pebs.c
+++ b/x86/pmu_pebs.c
@@ -117,6 +117,7 @@ static unsigned int get_adaptive_pebs_record_size(u64 pebs_data_cfg)
static void cnt_overflow(isr_regs_t *regs)
{
+ apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
apic_write(APIC_EOI, 0);
}
base-commit: 1ceee557f19a24455f162874586a0df5eaf53221
--
2.42.0.582.g8ccd20d70d-goog
