On Mon, Sep 25, 2023, Jim Mattson wrote: > On Fri, Sep 22, 2023 at 11:22 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote: > >The SDM doesn't explicitly state that mask bit is left > > unset in these cases, but my reading of > > > > When the local APIC handles a performance-monitoring counters interrupt, it > > automatically sets the mask flag in the LVT performance counter register. > > > > is that there has to be an actual interrupt. > > I assume you mean an actual interrupt from the APIC, not an actual PMI > to the APIC. Yeah. > I would argue that one way of "handling" a performance-monitoring > counters interrupt is to do nothing with it, but apparently I'm wrong. > At least, if I set the delivery mode in LVTPC to the illegal value of > 6, I never see the LVTPC.MASK bit get set. Heh, you could complain to Intel and see if they'll change "handles" to "delivers" :-)
