On Tue, Sep 19, 2023 at 12:56 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > Hey Anup, > > On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote: > > The Veyron-V1 CPU supports custom conditional arithmetic and > > conditional-select/move operations referred to as XVentanaCondOps > > extension. In fact, QEMU RISC-V also has support for emulating > > XVentanaCondOps extension. > > > > Let us detect XVentanaCondOps extension from ISA string available > > through DT or ACPI. > > > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > 3 files changed, 9 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 36ff6749fbba..cad8ef68eca7 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -171,6 +171,13 @@ properties: > > memory types as ratified in the 20191213 version of the privileged > > ISA specification. > > > > + - const: xventanacondops > > + description: | > > + The Ventana specific XVentanaCondOps extension for conditional > > + arithmetic and conditional-select/move operations defined by the > > + Ventana custom extensions specification v1.0.1 (or higher) at > > + https://github.com/ventanamicro/ventana-custom-extensions/releases. > > + > > For this and the next patch, the binding change needs to be split out > from the code. checkpatch should've complained about it. Okay, I will split this patch. > > > - const: zba > > description: | > > The standard Zba bit-manipulation extension for address generation > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 0f520f7d058a..b7efe9e2fa89 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -59,6 +59,7 @@ > > #define RISCV_ISA_EXT_ZIFENCEI 41 > > #define RISCV_ISA_EXT_ZIHPM 42 > > #define RISCV_ISA_EXT_SMSTATEEN 43 > > +#define RISCV_ISA_EXT_XVENTANACONDOPS 44 > > > > #define RISCV_ISA_EXT_MAX 64 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3755a8c2a9de..3a31d34fe709 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), > > I've been banging on for a bit about people doing weird stuff to detect > their vendor extensions, so nice to see it being done properly :) > > > Cheers, > Conor. > > > }; > > > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); > > -- > > 2.34.1 > > Regards, Anup
