On Mon, Sep 04, 2023 at 09:53:43AM +0000, Manali Shukla wrote:
>@@ -1207,6 +1241,29 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
> /* No need to intercept these MSRs */
> set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
> set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
>+
>+ /*
>+ * If hardware supports VIBS then no need to intercept IBS MSRS
>+ * when VIBS is enabled in guest.
>+ */
>+ if (vibs) {
>+ if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_IBS)) {
>+ svm_ibs_msr_interception(svm, false);
>+ svm->ibs_enabled = true;
>+
>+ /*
>+ * In order to enable VIBS, AVIC/VNMI must be enabled to handle the
>+ * interrupt generated by IBS driver. When AVIC is enabled, once
>+ * data collection for IBS fetch/op block for sampled interval
>+ * provided is done, hardware signals VNMI which is generated via
>+ * AVIC which uses extended LVT registers. That is why extended LVT
>+ * registers are initialized at guest startup.
>+ */
>+ kvm_apic_init_eilvt_regs(vcpu);
>+ } else {
>+ svm->ibs_enabled = false;
The interception should be enabled for IBS MSRs in the else branch. see:
https://lore.kernel.org/all/ZJYzPn7ipYfO0fLZ@xxxxxxxxxx/
>+ }
>+ }
> }
> }
>
>@@ -2888,6 +2945,11 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> case MSR_AMD64_DE_CFG:
> msr_info->data = svm->msr_decfg;
> break;
>+
>+ case MSR_AMD64_IBSCTL:
>+ rdmsrl(MSR_AMD64_IBSCTL, msr_info->data);
>+ break;
"When AVIC is enabled, IBS LVT entry (Extended Interrupt 0 LVT) message type
should be programmed to INTR or NMI."
It implies that AVIC always uses extended LVT 0 when issuing IBS interrupts if
IBS virtualization is enabled. Right? If yes, KVM should emulate the LvtOffset
in guest's IBS_CTL MSR as 0. Returning the hardware value here is error-prone.
