From: Santosh Shukla <santosh.shukla@xxxxxxx> Local interrupts can be extended to include more LVT registers in order to allow additional interrupt sources, like Instruction Based Sampling (IBS). The Extended APIC feature register indicates the number of extended Local Vector Table(LVT) registers in the local APIC. Currently, there are 4 extended LVT registers available which are located at APIC offsets (500h-530h). The EXTLVT feature bit changes the behavior associated with reading and writing an extended LVT register. When the EXTLVT feature is enabled, a write to an extended LVT register changes from a fault style #VMEXIT to a trap style #VMEXIT and a read of an extended LVT register no longer triggers a #VMEXIT. Please refer to Section 16.4.5 in AMD Programmer's Manual Volume 2 for more details on EXTLVT. https://bugzilla.kernel.org/attachment.cgi?id=304653 Presence of the EXTLVT feature is indicated via CPUID function 0x8000000A_EDX[27]. Signed-off-by: Santosh Shukla <santosh.shukla@xxxxxxx> Signed-off-by: Manali Shukla <manali.shukla@xxxxxxx> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b4ecbf78d8b..2e4624fa6e4e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -374,6 +374,7 @@ #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */ +#define X86_FEATURE_EXTLVT (15*32+27) /* "" EXTLVT */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ -- 2.34.1
