Hi Marc, On Tue, Aug 8, 2023 at 4:47 AM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > HFGITR_EL2 traps a bunch of instructions for which we don't have > encodings yet. Add them. > > Reviewed-by: Miguel Luis <miguel.luis@xxxxxxxxxx> > Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx> > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx> > --- > arch/arm64/include/asm/sysreg.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index bb5a0877a210..6d9d7ac4b31c 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -735,6 +735,13 @@ > #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) > #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) > > +/* Misc instructions */ > +#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) > +#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) > +#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) > +#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) > +#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) > + > /* Common SCTLR_ELx flags. */ > #define SCTLR_ELx_ENTP2 (BIT(60)) > #define SCTLR_ELx_DSSBS (BIT(44)) > -- > 2.34.1 > > Reviewed-by: Jing Zhang <jingzhangos@xxxxxxxxxx> Jing
