On Wed, Aug 09, 2023 at 09:48:29AM +0100, Marc Zyngier wrote: [...] > Another question is how the same thing is handled on x86? Maybe they > don't suffer from this problem thanks to specific architectural > features, but it'd be good to find out, as this may guide the > implementation in a different way. I'm pretty sure the bug here is arm64 specific. x86 (at least on intel) fetches the guest PMU context from the perf driver w/ irqs disabled immediately before entering the guest (see atomic_switch_perf_msrs()). -- Thanks, Oliver
