Hi Marc, > On 28 Jul 2023, at 08:29, Marc Zyngier <maz@xxxxxxxxxx> wrote: > > As we're about to implement full support for FEAT_FGT, add the > full HDFGRTR_EL2 and HDFGWTR_EL2 layouts. > > Reviewed-by: Mark Brown <broonie@xxxxxxxxxx> > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/sysreg.h | 2 - > arch/arm64/tools/sysreg | 129 ++++++++++++++++++++++++++++++++ > 2 files changed, 129 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e2357529c633..6d3d16fac227 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -497,8 +497,6 @@ > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > > #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > -#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) > -#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 65866bf819c3..2517ef7c21cf 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -2156,6 +2156,135 @@ Field 1 ICIALLU > Field 0 ICIALLUIS > EndSysreg > > +Sysreg HDFGRTR_EL2 3 4 3 1 4 > +Field 63 PMBIDR_EL1 > +Field 62 nPMSNEVFR_EL1 > +Field 61 nBRBDATA > +Field 60 nBRBCTL > +Field 59 nBRBIDR > +Field 58 PMCEIDn_EL0 > +Field 57 PMUSERENR_EL0 > +Field 56 TRBTRG_EL1 > +Field 55 TRBSR_EL1 > +Field 54 TRBPTR_EL1 > +Field 53 TRBMAR_EL1 > +Field 52 TRBLIMITR_EL1 > +Field 51 TRBIDR_EL1 > +Field 50 TRBBASER_EL1 > +Res0 49 > +Field 48 TRCVICTLR > +Field 47 TRCSTATR > +Field 46 TRCSSCSRn > +Field 45 TRCSEQSTR > +Field 44 TRCPRGCTLR > +Field 43 TRCOSLSR > +Res0 42 > +Field 41 TRCIMSPECn > +Field 40 TRCID > +Res0 39:38 > +Field 37 TRCCNTVRn > +Field 36 TRCCLAIM > +Field 35 TRCAUXCTLR > +Field 34 TRCAUTHSTATUS > +Field 33 TRC > +Field 32 PMSLATFR_EL1 > +Field 31 PMSIRR_EL1 > +Field 30 PMSIDR_EL1 > +Field 29 PMSICR_EL1 > +Field 28 PMSFCR_EL1 > +Field 27 PMSEVFR_EL1 > +Field 26 PMSCR_EL1 > +Field 25 PMBSR_EL1 > +Field 24 PMBPTR_EL1 > +Field 23 PMBLIMITR_EL1 > +Field 22 PMMIR_EL1 > +Res0 21:20 > +Field 19 PMSELR_EL0 > +Field 18 PMOVS > +Field 17 PMINTEN > +Field 16 PMCNTEN > +Field 15 PMCCNTR_EL0 > +Field 14 PMCCFILTR_EL0 > +Field 13 PMEVTYPERn_EL0 > +Field 12 PMEVCNTRn_EL0 > +Field 11 OSDLR_EL1 > +Field 10 OSECCR_EL1 > +Field 9 OSLSR_EL1 > +Res0 8 > +Field 7 DBGPRCR_EL1 > +Field 6 DBGAUTHSTATUS_EL1 > +Field 5 DBGCLAIM > +Field 4 MDSCR_EL1 > +Field 3 DBGWVRn_EL1 > +Field 2 DBGWCRn_EL1 > +Field 1 DBGBVRn_EL1 > +Field 0 DBGBCRn_EL1 > +EndSysreg > + > +Sysreg HDFGWTR_EL2 3 4 3 1 5 > +Res0 63 > +Field 62 nPMSNEVFR_EL1 > +Field 61 nBRBDATA > +Field 60 nBRBCTL > +Res0 59:58 > +Field 57 PMUSERENR_EL0 > +Field 56 TRBTRG_EL1 > +Field 55 TRBSR_EL1 > +Field 54 TRBPTR_EL1 > +Field 53 TRBMAR_EL1 > +Field 52 TRBLIMITR_EL1 > +Res0 51 > +Field 50 TRBBASER_EL1 > +Field 49 TRFCR_EL1 > +Field 48 TRCVICTLR > +Res0 47 > +Field 46 TRCSSCSRn > +Field 45 TRCSEQSTR > +Field 44 TRCPRGCTLR > +Res0 43 > +Field 42 TRCOSLAR > +Field 41 TRCIMSPECn > +Res0 40:38 > +Field 37 TRCCNTVRn > +Field 36 TRCCLAIM > +Field 35 TRCAUXCTLR > +Res0 34 > +Field 33 TRC > +Field 32 PMSLATFR_EL1 > +Field 31 PMSIRR_EL1 > +Res0 30 > +Field 29 PMSICR_EL1 > +Field 28 PMSFCR_EL1 > +Field 27 PMSEVFR_EL1 > +Field 26 PMSCR_EL1 > +Field 25 PMBSR_EL1 > +Field 24 PMBPTR_EL1 > +Field 23 PMBLIMITR_EL1 > +Res0 22 > +Field 21 PMCR_EL0 > +Field 20 PMSWINC_EL0 > +Field 19 PMSELR_EL0 > +Field 18 PMOVS > +Field 17 PMINTEN > +Field 16 PMCNTEN > +Field 15 PMCCNTR_EL0 > +Field 14 PMCCFILTR_EL0 > +Field 13 PMEVTYPERn_EL0 > +Field 12 PMEVCNTRn_EL0 > +Field 11 OSDLR_EL1 > +Field 10 OSECCR_EL1 > +Res0 9 > +Field 8 OSLAR_EL1 > +Field 7 DBGPRCR_EL1 > +Res0 6 > +Field 5 DBGCLAIM > +Field 4 MDSCR_EL1 > +Field 3 DBGWVRn_EL1 > +Field 2 DBGWCRn_EL1 > +Field 1 DBGBVRn_EL1 > +Field 0 DBGBCRn_EL1 > +EndSysreg > + Reviewed-by: Miguel Luis <miguel.luis@xxxxxxxxxx> Thanks Miguel > Sysreg ZCR_EL2 3 4 1 2 0 > Fields ZCR_ELx > EndSysreg > -- > 2.34.1 >
