On 7/27/2023 11:27 AM, Chao Gao wrote:
On Thu, Jul 20, 2023 at 11:03:48PM -0400, Yang Weijiang wrote:
/*
* Writes msr value into the appropriate "register".
* Returns 0 on success, non-0 otherwise.
@@ -2427,7 +2439,16 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
#define CET_LEG_BITMAP_BASE(data) ((data) >> 12)
#define CET_EXCLUSIVE_BITS (CET_SUPPRESS | CET_WAIT_ENDBR)
case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP:
- return kvm_set_msr_common(vcpu, msr_info);
+ if (kvm_set_msr_common(vcpu, msr_info))
+ return 1;
+ /*
+ * Write to the base SSP MSRs should happen ahead of toggling
+ * of IA32_S_CET.SH_STK_EN bit.
Is this a requirement from SDM? And how is this related to the change below?
No, after a second thought, the usage of the supervisor SSPs doesn't
necessary mean
supervisor SHSTK is being enabled, e.g., used as some HW registers. I'll
remove it.
Note that PLx_SSP MSRs are linear addresses of shadow stacks for different CPLs.
I may think using the page at 0 (assuming 0 is the reset value of PLx SSP) is
allowed in architecture although probably no kernel will do so.
I don't understand why this comment is needed. I suggest dropping it.
will drop it, thanks!
+ */
+ if (msr_index != MSR_IA32_PL3_SSP && data) {
+ vmx_disable_write_intercept_sss_msr(vcpu);
+ wrmsrl(msr_index, data);
+ }
