Hi Marc,
On 7/12/23 16:57, Marc Zyngier wrote:
> Add the 5 registers covering FEAT_FGT. The AMU-related registers
> are currently left out as we don't have a plan for them. Yet.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> ---
> arch/arm64/include/asm/kvm_host.h | 5 +++++
> arch/arm64/kvm/sys_regs.c | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 8b6096753740..1200f29282ba 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -400,6 +400,11 @@ enum vcpu_sysreg {
> TPIDR_EL2, /* EL2 Software Thread ID Register */
> CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
> SP_EL2, /* EL2 Stack Pointer */
> + HFGRTR_EL2,
> + HFGWTR_EL2,
> + HFGITR_EL2,
> + HDFGRTR_EL2,
> + HDFGWTR_EL2,
> CNTHP_CTL_EL2,
> CNTHP_CVAL_EL2,
> CNTHV_CTL_EL2,
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 3a6f678ca67d..f88cd1390998 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -2367,6 +2367,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
> EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
> EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
> + EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
> + EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
> + EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
> EL2_REG(HACR_EL2, access_rw, reset_val, 0),
>
> EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
> @@ -2376,6 +2379,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
>
> { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
> + EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
> + EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
> EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
> EL2_REG(ELR_EL2, access_rw, reset_val, 0),
> { SYS_DESC(SYS_SP_EL1), access_sp_el1},
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Eric
