On Thu, Jul 20, 2023 at 06:39:25PM +1000, Alistair Popple wrote: > The invalidate_range() is going to become an architecture specific mmu > notifier used to keep the TLB of secondary MMUs such as an IOMMU in > sync with the CPU page tables. Currently it is called from separate > code paths to the main CPU TLB invalidations. This can lead to a > secondary TLB not getting invalidated when required and makes it hard > to reason about when exactly the secondary TLB is invalidated. > > To fix this move the notifier call to the architecture specific TLB > maintenance functions for architectures that have secondary MMUs > requiring explicit software invalidations. > > This fixes a SMMU bug on ARM64. On ARM64 PTE permission upgrades > require a TLB invalidation. This invalidation is done by the > architecutre specific ptep_set_access_flags() which calls > flush_tlb_page() if required. However this doesn't call the notifier > resulting in infinite faults being generated by devices using the SMMU > if it has previously cached a read-only PTE in it's TLB. > > Moving the invalidations into the TLB invalidation functions ensures > all invalidations happen at the same time as the CPU invalidation. The > architecture specific flush_tlb_all() routines do not call the > notifier as none of the IOMMUs require this. > > Signed-off-by: Alistair Popple <apopple@xxxxxxxxxx> > Suggested-by: Jason Gunthorpe <jgg@xxxxxxxx> > Tested-by: SeongJae Park <sj@xxxxxxxxxx> > --- > arch/arm64/include/asm/tlbflush.h | 5 +++++ > arch/powerpc/include/asm/book3s/64/tlbflush.h | 1 + > arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 1 + > arch/powerpc/mm/book3s64/radix_tlb.c | 6 ++++++ > arch/x86/include/asm/tlbflush.h | 2 ++ > arch/x86/mm/tlb.c | 2 ++ > include/asm-generic/tlb.h | 1 - > 7 files changed, 17 insertions(+), 1 deletion(-) Reviewed-by: Jason Gunthorpe <jgg@xxxxxxxxxx> Jason
