> From: Anshuman Khandual <anshuman.khandual@xxxxxxx> > Sent: Wednesday, July 19, 2023 11:04 AM > > On 7/18/23 13:26, Alistair Popple wrote: > > The main change is to move secondary TLB invalidation mmu notifier > > callbacks into the architecture specific TLB flushing functions. This > > makes secondary TLB invalidation mostly match CPU invalidation while > > still allowing efficient range based invalidations based on the > > existing TLB batching code. > > > > ========== > > Background > > ========== > > > > The arm64 architecture specifies TLB permission bits may be cached and > > therefore the TLB must be invalidated during permission upgrades. For > > the CPU this currently occurs in the architecture specific > > ptep_set_access_flags() routine. > > > > Secondary TLBs such as implemented by the SMMU IOMMU match the CPU > > architecture specification and may also cache permission bits and > > require the same TLB invalidations. This may be achieved in one of two > > ways. > > > > Some SMMU implementations implement broadcast TLB maintenance > > (BTM). This snoops CPU TLB invalidates and will invalidate any > > secondary TLB at the same time as the CPU. However implementations are > > not required to implement BTM. > > So, the implementations with BTM do not even need a MMU notifier callback > for secondary TLB invalidation purpose ? Perhaps mmu_notifier_register() > could also be skipped for such cases i.e with ARM_SMMU_FEAT_BTM > enabled ? > Out of curiosity. How does BTM work with device tlb? Can SMMU translate a TLB broadcast request (based on ASID) into a set of PCI ATS invalidation requests (based on PCI requestor ID and PASID) in hardware? If software intervention is required then it might be the reason why mmu notifier cannot be skipped. With BTM enabled it just means the notifier callback can skip iotlb invalidation...
